Scheduling is a very important problem in architectural synthesis. While a sequencing graph does a good job at capturing the order of operation and dependencies among these operations but scheduling is responsible for annotating the start time of these operation also remember that the scheduling has to be aware that concurrency is possible but only when the ops are not dependent and can be parallelized so the behavior is preserved.

Scheduling determines the concurrency of the resulting implementation and therefore it affects its performance. By the same token at any given point of time the total number of concurrent operations of any given type at any step of the schedule is a lower bound on the number of required hardware resources of that type. So the choice of schedule also affects the area of the implementation.

Continuing on the discussion from above, the scheduling graph with resource bounds are done in order to meet area constraints. when the number of resources are bounded even if there are parallel operation we will have to serialize the extra operation as no resources are available for computation. A bare minimal case is only one operation available in one go in such a case execution is linear.

Area/latency trade-off points can be derived as solutions to constrained scheduling problems for desired values of the cycle-time. The area evaluation is just the weighted sum of all the resource in resource dominated circuit whereas for other circuits we need to consider the the corresponding to steering logic, registers, wiring and control area. # A model for the scheduling problems In the following section we will be using a non-hierarchical sequencing graph model.